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Internship: EDA Tooling for Design for Test

NXP Semiconductors N.V.  enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 30,000 employees in more than 30 countries and posted revenue of $9.41 billion in 2018. 

Would you like to gain industrial experience at a multinational organization like NXP?

Would you like to work on a real development case?

Well, within the DFT (Design For Test) team in Eindhoven we are looking for an intern that can help us with further improving our DFT approach.

Your subject area

NXP has many solutions to support the NXP IC designs teams with Design for Test. Solutions varying from creating design- for-test hardware, analysis of the design’s industrial testability all the way to creation of test vectors. These solutions all contribute to the high quality of NXP’s products.

Digital logic simulation is one of the basic techniques used for both IC design testability analysis as well as automatic test pattern generation. Currently, different simulation techniques are used in, on one hand an NXP proprietary tool and on the other hand an EDA vendor supplied tool. Using one single EDA vendor supplied technique, is preferred from an efficiency point of view. We are investigating how to standardize on a single logic simulation solution. Using this solution our next step will be to research how to validate that an IC with an asynchronous reset capability is not subjected to an asynchronous reset while in test mode and report violations back to the designer

Your responsibilities

  • Run experiments, replacing the proprietary logic simulation solution with an external EDA solution
  • Compare the results of the different solutions, performing a so called 'gap analysis'.
  • Time permitting, analyze the circumstances under which a design does not meet the standard for asynchronous reset
  • Work on an algorithm to create a report of violations
  • Work on implementing the algorithm in the NXP DFT tool set
  • What ’s in it for you

  • Freedom to choose on which of the two topics you would like to focus, in alignment with your coach
  • Opportunity to develop your skills (technical, soft skills, communication, etc.)
  • Gain experience in a multinational and diverse industrial environment
  • Opportunity to be a part of NXP’s Young Professional Talent Pool
  • Contributie to NXP’s success, by working on an assignment that will be deployed throughout NXP,
  • Extend your digital design knowledge and software engineering expertise
  • Who are we

    The "Digital Design Enablement" department, located in Eindhoven, is part of the Central Technology & Operation organization. The technical scope of the DTF & Test team within this department is focused on the NXP proprietary Design for Test Reference architecture and Design for Test Reference design flow. Combined, these two provide a well-documented and supported standard approach, broadly used throughout NXP to ensure robust and reliable testability of our products.

    Your profile

  • Master student in Electrotechnical engineering or Computer and Software engineering
  • Basic knowledge of digital electronic design (FlipFlops, gates, logic)
  • Basic knowledge of programming
  • Effective communication skills in Dutch or English
  • Duration

    The duration of the internship will be a minimum of six months to start asap. You will work for 40 hours a week.

    Please note that in order to be considered for an internship, you need to be registered as a student during the entire period.

    If you are as excited about this opportunity as we are, then we kindly invite you to apply!

    Internship: EDA Tooling for Design for Test

    NXP, Eindhoven
    Type contract: 
    Stage
    Functiecategorie: 
    Software Engineer, Elektrotechnish Ingenieur, Developer, Kwaliteit , Test Engineer, Ingenieur, Graduate Engineer, Industrieel Ingenieur, Junior IT Engineer, IT Consultant, Design Engineer, Quality Engineer, Technisch Consultant, R&D Engineer
    Opleidingsniveau: 
    Master
    Deadline sollicitatie: